US 12,328,876 B2
Three-dimensional semiconductor memory device
Seokcheon Baek, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Mar. 11, 2021, as Appl. No. 17/198,838.
Application 17/198,838 is a continuation of application No. 16/570,106, filed on Sep. 13, 2019, granted, now 10,978,475.
Claims priority of application No. 10-2018-0161618 (KR), filed on Dec. 14, 2018.
Prior Publication US 2021/0202522 A1, Jul. 1, 2021
Int. Cl. H10B 43/27 (2023.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/535 (2006.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 41/41 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01)
CPC H10B 43/27 (2023.02) [H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 23/535 (2013.01); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 41/41 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A three-dimensional semiconductor memory device, comprising:
a substrate including a cell array region and a pad region;
a stack extending from the cell array region to the pad region and comprising a first gate electrode on the substrate, a second gate electrode between the first gate electrode and the substrate, an insulating pattern between the first gate electrode and the second gate electrode, and a first edge pattern between the insulating pattern and the substrate; and
a first cell contact plug on the pad region that penetrates the first gate electrode, the insulating pattern, and the first edge pattern, the first cell contact plug comprising a step at a transition between a first width and a second width,
wherein the first cell contact plug has the first width at one portion horizontally adjacent to the first gate electrode and has the second width at another portion horizontally adjacent to the insulating pattern and the first edge pattern, and
wherein the first width is greater than the second width.