US 12,328,873 B2
Memory system
Takehiko Amaki, Kanagawa (JP); Yoshihisa Kojima, Kanagawa (JP); Toshikatsu Hida, Kanagawa (JP); Marie Grace Izabelle Angeles Sia, Kanagawa (JP); Riki Suzuki, Kanagawa (JP); and Shohei Asami, Kanagawa (JP)
Assigned to KIOXIA CORPORATION, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on May 2, 2024, as Appl. No. 18/653,241.
Application 18/653,241 is a continuation of application No. 18/314,527, filed on May 9, 2023, granted, now 12,029,031.
Application 18/314,527 is a continuation of application No. 17/725,638, filed on Apr. 21, 2022, granted, now 11,696,441, issued on Jul. 4, 2023.
Application 17/725,638 is a continuation of application No. 17/182,879, filed on Feb. 23, 2021, granted, now 11,348,934, issued on May 31, 2022.
Application 17/182,879 is a continuation of application No. 16/684,123, filed on Nov. 14, 2019, granted, now 10,964,712, issued on Mar. 30, 2021.
Application 16/684,123 is a continuation of application No. 16/052,238, filed on Aug. 1, 2018, granted, now 10,529,730, issued on Jan. 7, 2020.
Claims priority of application No. 2017-172150 (JP), filed on Sep. 7, 2017.
Prior Publication US 2024/0284668 A1, Aug. 22, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 41/27 (2023.01); G11C 7/04 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/16 (2006.01); G11C 16/26 (2006.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01)
CPC H10B 41/27 (2023.02) [G11C 7/04 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/107 (2013.01); G11C 16/16 (2013.01); G11C 16/26 (2013.01); H10B 43/27 (2023.02); H10B 43/35 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory system connectable to a host, comprising:
a nonvolatile memory that includes a plurality of blocks, each of the plurality of blocks being a unit of a data erase operation, each of the plurality of blocks including a plurality of word lines, the plurality of blocks including at least a plurality of first blocks, each of the plurality of first blocks storing valid user data; and
a controller electrically connected to the nonvolatile memory and configured to:
at a startup time of the memory system,
instruct the nonvolatile memory to perform a dummy read operation on at least one of the plurality of first blocks;
make sure that the dummy read operation on the at least one of the plurality of first blocks is finished before reading the valid user data therefrom in accordance with a read command received from the host; and
after the dummy read operation on the at least one of the plurality of first blocks is finished, instruct the nonvolatile memory to read the valid user data from the at least one of the plurality of first blocks in accordance with the read command received from the host, wherein
in the dummy read operation, the nonvolatile memory selects at least one of the plurality of blocks that is instructed by the controller, and applies a voltage higher than a ground voltage to each of the plurality of word lines included in the selected at least one of the plurality of blocks.