US 12,328,872 B2
Liner for V-NAND word line stack
Jacqueline S. Wrench, San Jose, CA (US); Yixiong Yang, Fremont, CA (US); Yong Wu, Sunnyvale, CA (US); Wei V. Tang, Santa Clara, CA (US); Srinivas Gandikota, Santa Clara, CA (US); Yongjing Lin, San Jose, CA (US); Karla M Bernal Ramos, San Jose, CA (US); and Shih Chung Chen, Cupertino, CA (US)
Assigned to Applied Materials, Inc., Santa Clara, CA (US)
Filed by Applied Materials, Inc., Santa Clara, CA (US)
Filed on Sep. 9, 2022, as Appl. No. 17/941,421.
Application 17/941,421 is a division of application No. 16/876,280, filed on May 18, 2020, granted, now 11,476,267.
Claims priority of provisional application 62/852,396, filed on May 24, 2019.
Prior Publication US 2023/0005945 A1, Jan. 5, 2023
Int. Cl. H10B 41/27 (2023.01); C23C 16/06 (2006.01); C23C 16/455 (2006.01); C23C 16/50 (2006.01); H01L 21/285 (2006.01); H01L 21/311 (2006.01); H01L 21/67 (2006.01); H10D 30/68 (2025.01); H10D 64/01 (2025.01)
CPC H10B 41/27 (2023.02) [C23C 16/06 (2013.01); C23C 16/45525 (2013.01); C23C 16/50 (2013.01); H01L 21/28568 (2013.01); H01L 21/31116 (2013.01); H01L 21/67167 (2013.01); H01L 21/67207 (2013.01); H10D 30/6891 (2025.01); H10D 64/035 (2025.01)] 7 Claims
OG exemplary drawing
 
1. A memory structure comprising:
a plurality of alternating layers of a silicon material and a metal gate, the metal gate comprising a conformal barrier layer on the silicon material, a conformal α-tungsten (W) layer directly on the conformal barrier layer, and a bulk tungsten layer on the conformal α-tungsten (W) layer,
the conformal barrier layer comprising a metal nitride having a chemical formula of TiXN or TaXN, X being selected from one or more of aluminum (Al), silicon (Si), tungsten (W), lanthanum (La), yttrium (Yt), strontium (Sr), or magnesium (Mg), and
the conformal barrier layer having a thickness in a range of from 5 Å to 15 Å; and
a memory hole channel formed through the plurality of alternating layers of the silicon material and the metal, and the memory hole channel having a conformal layer of a poly-silicon material deposited directly on a first surface, a second surface, and a third surface of the memory hole channel.