| CPC H10B 12/50 (2023.02) [H10B 12/0335 (2023.02); H10B 12/09 (2023.02); H10B 12/315 (2023.02); H10B 12/34 (2023.02)] | 18 Claims |
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1. A semiconductor device, comprising:
a substrate including a cell region and a peripheral region;
a plurality of lower electrodes on the cell region of the substrate;
a dielectric layer on surfaces of the lower electrodes;
a metal containing layer directly on a surface of the dielectric layer, the metal containing layer disposed along the surfaces of the dielectric layer;
at least one support layer pattern between and contacting adjacent lower electrodes of the plurality of lower electrodes;
a silicon germanium layer on the metal containing layer, the silicon germanium layer having a first portion having a flat upper surface and a second portion having a vertical surface positioned at a boundary between the cell region and the peripheral region;
a stacked structure including a metal plate pattern and a polishing stop layer pattern sequentially stacked on the silicon germanium layer, the stacked structure having openings at least partially exposing the flat upper surface of the silicon germanium layer on the cell region, the stacked structure covering the first portion and the second portion of the silicon germanium layer, and the metal plate pattern contacting the silicon germanium layer; and
upper contact plugs physically contacting the first portion of the silicon germanium layer,
wherein the upper contact plugs have an uppermost surface farther away from the substrate than an uppermost surface of the stacked structure,
wherein the upper contact plugs passing through the opening of the stacked structure, and
wherein the upper contact plugs are spaced apart from the stacked structure including the metal plate pattern and the polishing stop layer pattern.
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11. A semiconductor device, comprising:
a substrate including a cell region and a peripheral region;
a plurality of lower electrodes on the cell region of the substrate;
at least one support layer pattern between and contacting adjacent lower electrodes of the plurality of lower electrodes;
a dielectric layer on surfaces of the lower electrodes and a surface of the at least one support layer pattern;
a metal containing layer directly on a surface of the dielectric layer, the metal containing layer disposed along the surface of the dielectric layer;
a silicon germanium layer on the dielectric layer, the silicon germanium layer including a flat upper surface positioned on the cell region and a vertical surface positioned at a boundary between the cell region and the peripheral region;
a stacked structure including a metal plate pattern and a polishing stop layer pattern sequentially stacked on the silicon germanium layer, the metal plate pattern contacting the silicon germanium layer, the stacked structure including openings at least partially exposing an upper surface of the silicon germanium layer on the cell region, and the stacked structure covering the flat upper surface and the vertical surface of the silicon germanium layer;
filling insulation patterns in the openings, respectively;
upper contact plugs physically contacting the flat upper surface of the silicon germanium layer,
a second insulating interlayer on the peripheral region; and
a third insulating interlayer on the polishing stop layer pattern, the filling insulation patterns, and the second insulating interlayer,
wherein an uppermost surface of the upper contact plugs is higher than an uppermost surface of the stacked structure, and
wherein the upper contact plugs extend through the third insulating interlayer and the filling insulating patterns.
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15. A semiconductor device, comprising:
a substrate including a cell region and a peripheral region;
a cell lower structure including bit line structures, contact plugs, and landing pads on the cell region of the substrate
a plurality of lower electrodes on the landing pads, respectively;
at least one support layer pattern between and contacting two adjacent lower electrodes of the plurality of lower electrodes;
a dielectric layer directly on surfaces of the lower electrodes;
a metal containing layer directly on a surface of the dielectric layer, the metal containing layer disposed along the surface of the dielectric layer;
a silicon germanium layer on the dielectric layer, the silicon germanium layer including a flat upper surface positioned on the cell region and a vertical surface positioned at a boundary between the cell region and the peripheral region;
a stacked structure including a metal plate pattern and a polishing stop layer pattern sequentially stacked on the silicon germanium layer, the metal plate pattern contacting the silicon germanium layer, the stacked structure including openings at least partially exposing an upper surface of the silicon germanium layer on the cell region, and the stacked structure covering the flat upper surface and the vertical surface of the silicon germanium layer;
filling insulation patterns in the openings, respectively;
an insulating interlayer on the polishing stop layer pattern, the filling insulation patterns, and a peripheral region, the insulating interlayer having a flat upper surface;
upper contact plugs extending through the insulating interlayer and the filling insulation patterns, the upper contact plugs physically contacting the flat upper surface of the silicon germanium layer,
wherein an uppermost surface of the upper contact plugs is higher than an uppermost surface of the stacked structure.
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