| CPC H10B 12/50 (2023.02) [H10B 12/09 (2023.02); H10B 12/315 (2023.02); H10B 12/482 (2023.02); H10B 12/485 (2023.02); H10D 64/021 (2025.01)] | 15 Claims |
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1. A semiconductor memory device comprising:
a substrate comprising a cell region and a peripheral region around the cell region;
a cell region isolation film in the substrate, the cell region isolation film defining the cell region, wherein the cell region isolation film is interposed between the cell region and the peripheral region;
a bit line structure on the cell region;
a first peripheral gate structure on the peripheral region of the substrate, the first peripheral gate structure comprising a first peripheral gate conduction film and a first peripheral capping film on the first peripheral gate conduction film;
a peripheral interlayer insulating film around the first peripheral gate structure and on the substrate, the peripheral interlayer insulating film being non-overlapping with the cell region in plan view;
an insertion interlayer insulating film on the peripheral interlayer insulating film and the first peripheral gate structure, the insertion interlayer insulating film comprising a material that is different from the peripheral interlayer insulating film;
a block conduction structure comprising a block capping film on the a block conduction line; and
a cell interlayer insulating film on the cell region isolation film between the block conduction structure and the bit line structure,
wherein an upper face of the cell interlayer insulating film is closer to the substrate than an upper face of the block capping film,
wherein an upper face of the peripheral interlayer insulating film is closer to the substrate than an upper face of the first peripheral capping film,
wherein the first peripheral gate structure further comprises a peripheral spacer on side walls of the first peripheral gate conduction film and the first peripheral capping film, and
wherein a height, with respect to an upper face of the substrate, of the upper face of an uppermost portion of the peripheral interlayer insulating film is less than a height, with respect to the upper face of the substrate, of an uppermost portion of the peripheral spacer.
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