US 12,328,867 B2
Memory devices having vertical transistors and methods for forming the same
Tao Yang, Wuhan (CN); Dongxue Zhao, Wuhan (CN); Yuancheng Yang, Wuhan (CN); Zhiliang Xia, Wuhan (CN); and Zongliang Huo, Wuhan (CN)
Assigned to YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed by YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed on Dec. 1, 2021, as Appl. No. 17/539,784.
Application 17/539,784 is a continuation of application No. PCT/CN2021/127790, filed on Oct. 31, 2021.
Prior Publication US 2023/0138205 A1, May 4, 2023
Int. Cl. H10B 12/00 (2023.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01); H10D 30/01 (2025.01); H10D 30/63 (2025.01)
CPC H10B 12/33 (2023.02) [H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H10B 12/036 (2023.02); H10B 12/05 (2023.02); H10B 12/482 (2023.02); H10D 30/025 (2025.01); H10D 30/63 (2025.01); H01L 2224/08145 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1436 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a vertical transistor comprising a semiconductor body extending in a first direction, the semiconductor body comprising a doped source, a doped drain, and a channel portion;
a storage unit coupled to a first terminal, the first terminal being one of the source and the drain; and
a bit line extending in a second direction perpendicular to the first direction and in contact with a second terminal, the second terminal being another one of the source and the drain that is formed on all sides of a protrusion of the semiconductor body, wherein the bit line is separated from the channel portion of the semiconductor body by the second terminal.