| CPC H10B 12/315 (2023.02) [H10B 12/0335 (2023.02); H10B 12/053 (2023.02); H10B 12/34 (2023.02); H10B 12/482 (2023.02)] | 20 Claims |
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1. A semiconductor device comprising:
an active pattern on a substrate;
a gate structure in an upper portion of the active pattern, the gate structure extending in a first direction that is parallel to an upper surface of the substrate;
a bit line structure extending in a second direction that is parallel to the upper surface of the substrate and is perpendicular to the first direction, an upper surface of a middle portion of the active pattern in a length direction of the active pattern being recessed toward the substrate, the bit line structure contacting the upper surface of the middle portion of the active pattern, and the bit line structure including a first conductive pattern, a diffusion barrier, a second conductive pattern and a capping pattern sequentially stacked on the substrate;
a lower spacer structure extending on a portion of a sidewall of the first conductive pattern of the bit line structure, the lower spacer structure including a first lower spacer and a second lower spacer sequentially stacked on the portion of the sidewall of the first conductive pattern of the bit line structure;
an upper spacer structure extending on a portion of a sidewall of the bit line structure, the lower spacer structure not covering the portion of the sidewall of the bit line structure, and the upper spacer structure including a first upper spacer, a second upper spacer, and a third upper spacer sequentially stacked on the portion of the sidewall of the bit line structure;
a contact plug structure on one of opposing end portions of the active pattern in the length direction of the active pattern, the contact plug structure including a lower contact plug, an ohmic contact pattern, a barrier layer and an upper contact plug sequentially stacked on the substrate; and
a capacitor on the contact plug structure,
wherein the first lower spacer contacts the portion of the sidewall of the first conductive pattern of the bit line structure and does not include nitrogen, and the second lower spacer includes a material different from that of the first lower spacer,
wherein the first upper spacer contacts the portion of the sidewall of the bit line structure and includes a material different from that of the first lower spacer, and
wherein each of the first, second, and third upper spacers directly contacts an upper surface of the lower spacer structure.
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