| CPC H10B 12/30 (2023.02) [H01L 23/528 (2013.01); H10B 12/03 (2023.02); H10B 12/05 (2023.02); H10B 12/482 (2023.02); H10D 1/692 (2025.01); H10D 30/6728 (2025.01); H10D 30/6729 (2025.01); H10D 30/6757 (2025.01)] | 18 Claims |
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1. A method of forming a memory device, comprising:
forming a stack comprising a plurality of conductive layers alternating with first insulating layers;
patterning the stack, wherein each conductive layer is patterned to form a bit line and an array of memory cell regions, each memory cell region comprising:
a transistor region having a sacrificial channel formed of the conductive layer; and
a capacitor region having a capacitor electrode formed of the conductive layer and connected to the sacrificial channel;
forming spacers along sidewalls of the bit lines;
disposing a second insulating layer over the patterned stack and the spacers;
forming first trenches through the second insulating layer to expose the transistor regions;
removing the sacrificial channel with an etching process to form a cavity;
disposing a semiconductor channel in the cavity;
disposing a gate dielectric over the semiconductor channel;
filling the first trenches with a conductive material to form a plurality of word lines;
forming second trenches through the second insulating layer to expose the capacitor regions;
disposing a capacitor dielectric over the exposed capacitor electrodes; and
filling the second trenches with a conductive material.
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