| CPC H10B 12/30 (2023.02) [H10B 12/05 (2023.02)] | 13 Claims |
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1. A 3D memory, comprising:
a plurality of layers of memory cells and a plurality of insulation layers stacked alternately in a first direction; wherein a memory cell of each layer comprises a conductive film layer, and the first direction is perpendicular to a substrate;
a hole penetrating through each of the insulation layers and each of the conductive film layers in the first direction;
a semiconductor layer extending onto a sidewall of the hole; wherein the semiconductor layer is a metal oxide semiconductor layer; and
a word line, wherein the word line is located in the hole, extends in the first direction and penetrates through the plurality of layers of memory cells, and is insulated from the semiconductor layer;
wherein the memory cell comprises a transistor, the transistor comprises a source, a drain in the conductive film layer, a gate which is part of the word line and extends in the first direction, wherein the gate is surrounded by the semiconductor layer, the semiconductor layer comprises a source contact region and a drain contact region arranged at intervals, a channel between the source contact region and the drain contact region is a horizontal channel; the source extends in a second direction and the drain extends in a third direction, the second direction is parallel to the substrate and the third direction is parallel to the substrate, and the second direction and the third direction intersect with each other; the conductive film layer comprises a sub-portion extending in the third direction, and an end of the source away from the semiconductor layer is surrounded by the sub-portion; and transistors of different layers share one semiconductor layer.
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