US 12,328,862 B2
Semiconductor structure and manufacturing method thereof
Shih-Han Hung, Taichung (TW); and Feng-Jung Chang, Taichung (TW)
Assigned to Winbond Electronics Corp., Taichung (TW)
Filed by Winbond Electronics Corp., Taichung (TW)
Filed on Dec. 1, 2022, as Appl. No. 18/073,478.
Prior Publication US 2024/0188277 A1, Jun. 6, 2024
Int. Cl. H10B 12/00 (2023.01)
CPC H10B 12/09 (2023.02) [H10B 12/315 (2023.02); H10B 12/34 (2023.02); H10B 12/50 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a substrate comprising a first region and a second region;
buried word line structures located in the substrate in the first region;
a transistor structure located on the substrate in the second region;
a first hard mask layer located on the transistor structure and having recesses;
hard mask marks located in the recesses;
a second hard mask layer located on the substrate in the first region and having openings; and
contacts located in the openings.