| CPC H10B 12/05 (2023.02) [H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H10B 12/482 (2023.02); H10B 12/488 (2023.02)] | 15 Claims |
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1. A manufacturing method for a semiconductor device comprising memory cells of different layers stacked and distributed in a direction perpendicular to a substrate, each memory cell comprising a transistor, the manufacturing method comprising:
sequentially and alternately depositing sacrificial layers and insulation layers on the substrate to obtain a stacked structure;
forming in the stacked structure a plurality of via holes penetrating through the stacked structure and distributed at intervals in a first direction, and forming dummy word lines in the via holes;
forming a first trench penetrating through the stacked structure every two via holes apart in the stacked structure, wherein the first trench extends in a second direction, and a plurality of insulation layers and a plurality of sacrificial layers alternately stacked are distributed between any two adjacent first trenches;
forming a plurality of grooves by re-etching the plurality of insulation layers within the first trench, wherein two grooves of each insulation layer in two first trenches respectively expose partial side walls of a dummy word line;
forming conductive layers within corresponding two grooves of each insulation layer, wherein a plurality of conductive layers corresponding to different insulation layers are insulated from each other, and a conductive layer in each groove surrounds an exposed dummy word line; and
disconnecting the conductive layer surrounding the dummy word line in each groove in the second direction, wherein disconnected two parts are located at opposite sides of the dummy word line, and the disconnected two parts are used for forming a first electrode and a second electrode of the transistor.
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