US 12,328,860 B2
Semiconductor device with increased unity density
You-Cheng Xiao, Taichung County (TW); Jhih-Siang Hu, New Taipei (TW); Ru-Yu Wang, New Taipei (TW); Jung-Hsuan Chen, Hsinchu (TW); and Ting-Wei Chiang, New Taipei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed on Dec. 15, 2022, as Appl. No. 18/066,733.
Application 18/066,733 is a division of application No. 17/035,438, filed on Sep. 28, 2020, granted, now 11,552,085.
Prior Publication US 2023/0124337 A1, Apr. 20, 2023
Int. Cl. H10B 10/00 (2023.01); H01L 23/528 (2006.01)
CPC H10B 10/18 (2023.02) [H01L 23/5286 (2013.01); H10B 10/12 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
at least one memory cell; and
at least one logic cell disposed next to the at least one memory cell, comprising:
a plurality of fins, wherein the plurality of fins are separated into a plurality of fin groups for forming transistors,
wherein a distance between two adjacent groups of the plurality of fin groups is different from a distance between another two adjacent groups of the plurality of fin groups,
a first part of the plurality of fins are arranged on a plurality of fin grids,
a second part of the plurality of fins are separated from the plurality of fin grids, and
the plurality of fin grids are arranged in parallel and extend across regions of the at least one memory cell and the at least one logic cell,
the at least one logic cell further comprises a first conductive rail, a second conductive rail,
the first conductive rail is overlapped with the plurality of fins in a layout view, and
the second conductive rail is separated from the plurality of fins in the layout view.