US 12,328,859 B2
Stacked FET SRAM
Ruilong Xie, Niskayuna, NY (US); Carl Radens, LaGrangeville, NY (US); Albert M. Chu, Nashua, NH (US); Brent A. Anderson, Jericho, VT (US); Junli Wang, Slingerlands, NY (US); Julien Frougier, Albany, NY (US); and Ravikumar Ramachandran, Pleasantville, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Jun. 30, 2022, as Appl. No. 17/854,780.
Prior Publication US 2024/0008242 A1, Jan. 4, 2024
Int. Cl. H10B 10/00 (2023.01)
CPC H10B 10/125 (2023.02) 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first stacked field effect transistor device present in a first device area, the first stacked field effect transistor device comprising two top transistors stacked above a single bottom transistor;
a full gate cut structure located at the periphery of the first device area, and separating the first device area from an adjacent second device area;
a top gate cut structure separating the two top transistors from each other; and
a bottom gate cut structure located laterally adjacent to the single bottom transistor and beneath one of the top transistors.