US 12,328,858 B2
Silicon-on-insulator semiconductor device with a static random access memory circuit
Olivier Weber, Grenoble (FR); Kedar Janardan Dhori, Ghaziabad (IN); Promod Kumar, Greater Noida (IN); Shafquat Jahan Ahmed, Greater Noida (IN); Christophe Lecocq, Varces (FR); and Pascal Urard, Theys (FR)
Assigned to STMICROELECTRONICS FRANCE, Montrouge (FR); STMICROELECTRONICS (CROLLES 2) SAS, Crolles (FR); and STMICROELECTRONICS INTERNATIONAL N.V., Geneva (CH)
Filed by STMicroelectronics France, Montrouge (FR); STMicroelectronics (Crolles 2) SAS, Crolles (FR); and STMicroelectronics International N.V., Geneva (CH)
Filed on Jul. 5, 2023, as Appl. No. 18/347,435.
Claims priority of application No. 2206897 (FR), filed on Jul. 6, 2022.
Prior Publication US 2024/0015945 A1, Jan. 11, 2024
Int. Cl. G11C 11/417 (2006.01); H10B 10/00 (2023.01)
CPC H10B 10/12 (2023.02) [G11C 11/417 (2013.01); H10B 10/18 (2023.02)] 22 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a carrier substrate;
a buried dielectric region overlying the carrier substrate;
a semiconductor film separated from the carrier substrate by the buried dielectric region; and
NMOS transistors and PMOS transistors disposed at a surface of the semiconductor film and coupled together to form a static random access memory (SRAM) cell, the NMOS transistors and the PMOS transistors each comprising a gate dielectric layer having a thickness greater than 3 nanometers and an active region in the semiconductor film, the active region of the PMOS transistors comprising a silicon-germanium alloy.