US 12,328,837 B2
Chassis architecture and server comprising same
Jingxian Zhu, Jiangsu (CN); Zhencai Cao, Jiangsu (CN); Zhanyang Li, Jiangsu (CN); and Xiuzhong Yin, Jiangsu (CN)
Assigned to SUZHOU METABRAIN INTELLIGENT TECHNOLOGY CO., LTD., Jiangsu (CN)
Appl. No. 18/873,670
Filed by SUZHOU METABRAIN INTELLIGENT TECHNOLOGY CO., LTD., Jiangsu (CN)
PCT Filed Aug. 31, 2023, PCT No. PCT/CN2023/116213
§ 371(c)(1), (2) Date Dec. 10, 2024,
PCT Pub. No. WO2024/146156, PCT Pub. Date Jul. 11, 2024.
Claims priority of application No. 202310005573.2 (CN), filed on Jan. 4, 2023.
Prior Publication US 2025/0169017 A1, May 22, 2025
Int. Cl. H05K 7/20 (2006.01); G06F 1/18 (2006.01); G06F 1/20 (2006.01); H05K 7/14 (2006.01)
CPC H05K 7/1488 (2013.01) [G06F 1/189 (2013.01); G06F 1/20 (2013.01); H05K 7/20736 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A chassis architecture, comprising:
a PCIE (Peripheral Component Interface Express) module layer, comprising a bottom plate and two side plates connected to two sides of the bottom plate, a PCIE module installing area and a fan installing area being respectively provided at two ends of the bottom plate in an extending direction of the bottom plate, and the PCIE module installing area being configured for accommodating a plurality of PCIE modules;
a threading layer, provided above the PCIE module layer and corresponding to the PCIE module installing area, two sides of the threading layer being connected to the two side plates, the threading layer being provided with a plurality of first threading holes, the plurality of first threading holes being configured for allowing a passage of a PCIE cable connected to the plurality of PCIE modules, and an upper surface of the threading layer being configured for bearing the PCIE cable; and
a computing layer, provided above the threading layer, two sides of the computing layer being connected to the two side plates, the computing layer being provided with a mainboard installing area and a power supply installing area, the computing layer being provided with a plurality of second threading holes, and the plurality of second threading holes being configured for allowing the passage of the PCIE cable, so that the PCIE cable extends to the mainboard installing area and/or the power supply installing area.