US 12,328,827 B2
Protecting method for preventing solder crack failure in electronic product
Tsung-Lung Lin, Taipei (TW); Kuan-Yu Chen, Taipei (TW); and Yi-Chun Huang, Taipei (TW)
Assigned to SOLID STATE STORAGE TECHNOLOGY CORPORATION, Taipei (TW)
Filed by SOLID STATE STORAGE TECHNOLOGY CORPORATION, Taipei (TW)
Filed on Dec. 8, 2022, as Appl. No. 18/077,255.
Claims priority of application No. 202211204201.4 (CN), filed on Sep. 29, 2022.
Prior Publication US 2024/0114631 A1, Apr. 4, 2024
Int. Cl. H05K 3/34 (2006.01); G01R 31/28 (2006.01)
CPC H05K 3/3463 (2013.01) [G01R 31/2855 (2013.01); G01R 31/2874 (2013.01); G01R 31/2875 (2013.01); G01R 31/2877 (2013.01)] 10 Claims
OG exemplary drawing
 
9. A protecting method for preventing solder crack failure in a solid state device, the solid state device comprising a circuit board, a controller and plural non-volatile memory chips, the controller and the plural non-volatile memory chips being soldered on plural layout traces of the printed circuit board through a metallic solder material, the controller being electrically connected with the plural non-volatile memory chips, the protecting method comprising steps of:
confirming that a crack incidence rate of a metallic solder material in a printed circuit board is high; and
activating a protecting mechanism, wherein when an operating temperature of the solid state device reaches a first operating temperature, the controller controls the solid state device to enter and leave an idle mode multiple times and controls a time length in the idle mode, so that the operating temperature of the solid state device is decreased at a first average drop rate.