US 12,328,753 B2
Logical channel prioritization for data
Linhai He, San Diego, CA (US); Yuchul Kim, San Diego, CA (US); and Huilin Xu, Temecula, CA (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Jul. 15, 2022, as Appl. No. 17/813,018.
Prior Publication US 2024/0023155 A1, Jan. 18, 2024
Int. Cl. H04W 72/543 (2023.01); H04W 72/21 (2023.01); H04W 72/566 (2023.01)
CPC H04W 72/543 (2023.01) [H04W 72/21 (2023.01); H04W 72/569 (2023.01)] 26 Claims
OG exemplary drawing
 
12. An apparatus for wireless communication at a user equipment (UE), comprising:
memory; and
at least one processor coupled to the memory and configured to:
receive a configuration indicating priority levels for each of multiple logical channels;
schedule one or more packets for uplink transmission according to a priority level of a logical channel associated with a respective packet of the one or more packets;
adjust scheduling of the one or more packets for the uplink transmission in response to a residual delay budget of a packet exceeding a delay threshold; and
transmit the uplink transmission including at least one of the one or more packets based on the adjusted scheduling.