| CPC H04W 72/23 (2023.01) [H04W 72/1263 (2013.01); H04W 72/21 (2023.01)] | 14 Claims |

|
1. A terminal device, comprising:
one or more processors; and
one or more memories that stores a computer-readable instruction for causing, when executed by the one or more processors, the one or more processors to at least:
receive a plurality of scheduling request (SR) settings from a base station, wherein each of the plurality of SR settings corresponds to different combinations of a bandwidth, a time duration, and a periodicity, and each of the plurality of SR settings is capable of being used for transmission of a scheduling request in a cell served by the base station device;
select, in a case where data that is to be transmitted to the base station device is generated, one SR setting for use in transmission of the scheduling request to the base station device, from among the plurality of SR settings, wherein the terminal device can select the one SR setting from the plurality of SR settings without receiving from the base station an instruction that designates the one SR setting; and
transmit the scheduling request to the base station device with use of the one SR setting that was selected.
|