US 12,328,518 B2
Light detector
Tatsuya Kabe, Osaka (JP); Hideyuki Arai, Osaka (JP); Hisashi Aikawa, Osaka (JP); Yuki Sugiura, Osaka (JP); Akito Inoue, Osaka (JP); Mitsuyoshi Mori, Kyoto (JP); Kentaro Nakanishi, Nara (JP); and Yusuke Sakata, Osaka (JP)
Assigned to PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD., Osaka (JP)
Filed by Panasonic Intellectual Property Management Co., Ltd., Osaka (JP)
Filed on Dec. 15, 2023, as Appl. No. 18/541,932.
Application 18/541,932 is a continuation of application No. 17/486,495, filed on Sep. 27, 2021, granted, now 11,889,215.
Application 17/486,495 is a continuation of application No. PCT/JP2020/010235, filed on Mar. 10, 2020.
Claims priority of application No. 2019-063298 (JP), filed on Mar. 28, 2019.
Prior Publication US 2024/0121530 A1, Apr. 11, 2024
Int. Cl. H04N 25/75 (2023.01); H04N 25/766 (2023.01); H10F 39/00 (2025.01); H10F 39/18 (2025.01)
CPC H04N 25/75 (2023.01) [H04N 25/766 (2023.01); H10F 39/18 (2025.01); H10F 39/8037 (2025.01); H10F 39/811 (2025.01)] 11 Claims
OG exemplary drawing
 
1. A light detector in which a light receiving portion and a peripheral portion are provided on a semiconductor substrate, wherein:
the light receiving portion includes:
an n-type first region;
a p-type second semiconductor layer; and
a p-type first semiconductor layer,
the first region, the second semiconductor layer, and the first semiconductor layer are stacked in this order,
a maximum p-type impurity concentration in the first semiconductor layer is higher than a maximum p-type impurity concentration in the second semiconductor layer,
the peripheral portion includes:
a p-type first well;
an n-type third well;
an n-type fourth well;
an isolation; and
the first semiconductor layer,
the isolation contacts side portions of the third well and the fourth well, and
the third well surrounds at least one side portion and a bottom portion of the first well as viewed in a cross section.