| CPC H04L 9/3242 (2013.01) [H04L 9/0618 (2013.01); H04L 9/0836 (2013.01)] | 11 Claims |

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1. A memory processing apparatus comprising:
hardware, including a processor and memory;
memory address allocation unit implemented at least by the hardware and configured to allocate, to each of nodes in a tree structure configured to protect a memory, a memory address unique to the node;
tag generation unit implemented at least by the hardware and configured to (A) define, for each of the nodes in the tree structure, a connection of a value of the memory address unique to each of the nodes and a constant, as a nonce, (B) generate, for each of leaf nodes and a specific node, a tag by inputting the nonce of each of the nodes and a plaintext of which tampering with is to be detected into a message authentication code, or by inputting the nonce of each of the nodes and constants of a plurality of child nodes of each of the nodes into the message authentication code, and (C) generate, for each of nodes other than the leaf nodes and the specific node, a tag by inputting the nonce of each of the nodes, the nonce of the specific node, and the tag of the specific node into the message authentication code, the message authentication code being a code by which a partially-updatable tag can be output; and
node generation unit implemented at least by the hardware and configured to generate each of the nodes in the tree structure by using the constant as a local counter and combining at least the tag and the local counter.
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