US 12,328,365 B2
UART-hub design for multiple data transmission
Chia-Hung Hsu, Hsinchu (TW); Cheng-Hao Yao, Hsinchu (TW); Jyun-Ji Wang, Hsinchu (TW); and Yu-Lin Tsai, Hsinchu (TW)
Assigned to MEDIATEK INC., Hsinchu (TW)
Filed by MEDIATEK INC., Hsin-Chu (TW)
Filed on Jul. 13, 2023, as Appl. No. 18/221,402.
Claims priority of provisional application 63/368,898, filed on Jul. 20, 2022.
Claims priority of provisional application 63/439,161, filed on Jan. 16, 2023.
Prior Publication US 2024/0031438 A1, Jan. 25, 2024
Int. Cl. H04L 67/12 (2022.01); G06F 13/42 (2006.01); H04L 69/22 (2022.01)
CPC H04L 67/12 (2013.01) [G06F 13/4213 (2013.01); G06F 13/4282 (2013.01); H04L 69/22 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A multi-chip system, comprising:
a first chip, comprising:
a plurality of first application circuits, configured to generate a plurality of first data, respectively; and
a first universal asynchronous receiver/transmitter (UART) interface;
a second chip, comprising:
a plurality of second application circuits, configured to generate a plurality of second data, respectively; and
a second UART interface;
wherein the plurality of first data respectively generated by the plurality of first application circuits are transmitted to the second chip via the same first UART interface; and the plurality of second data respectively generated by the plurality of second application circuits are transmitted to the first chip via the same second UART interface.