US 12,328,249 B2
Device and method of intra-chip routing of neural tasks for operating system of brain-inspired computer
Fengjuan Wang, Hangzhou (CN); Pan Lv, Hangzhou (CN); Min Kang, Hangzhou (CN); Shuiguang Deng, Hangzhou (CN); Ying Li, Hangzhou (CN); and Gang Pan, Hangzhou (CN)
Assigned to ZHEJIANG LAB, Hangzhou (CN); and ZHEJIANG UNIVERSITY, Hangzhou (CN)
Appl. No. 18/267,402
Filed by ZHEJIANG LAB, Hangzhou (CN); and ZHEJIANG UNIVERSITY, Hangzhou (CN)
PCT Filed Feb. 14, 2023, PCT No. PCT/CN2023/075811
§ 371(c)(1), (2) Date Jun. 14, 2023,
PCT Pub. No. WO2023/173977, PCT Pub. Date Sep. 21, 2023.
Claims priority of application No. 202210249528.7 (CN), filed on Mar. 15, 2022.
Prior Publication US 2024/0372799 A1, Nov. 7, 2024
Int. Cl. H04L 45/122 (2022.01); H04L 49/109 (2022.01)
CPC H04L 45/122 (2013.01) [H04L 49/109 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A method of intra-chip routing of neural tasks for an operating system of a brain-inspired computer, wherein cores in a brain-inspired computing chip are constructed into a two-dimensional grid, each grid represents a core, each core is configured to store model data of neural tasks and to provide relay routing, and the method comprises the following steps:
at step 1, determining an area defined by target cores, and determining target cores in a row furthest from an edge routing area;
at step 2, determining whether the target cores need to be configured with relay routing;
at step 3, searching nearest edge routing cores in the edge routing area for all the target cores in the area defined by the target cores via a shortest step length manner, and performing step 5 after the searching is completed;
at step 4, configuring the target cores in a far-to-near principle, determining a coordinate of a starting search core from an area defined by the target cores that need to search for relay routing, and searching a maximum number of the target cores that relay routing cores in the brain-inspired computing chip support to be configured each time; for the target cores that need multi-level relays, searching multi-level relay routing cores and the nearest edge routing cores by a shortest path manner and a maximum step length of a single routing manner, until all the target cores in the area defined by the target cores that need to search for relay routing are configured; and
at step 5, packaging routing data and configuring the routing data into the brain-inspired computing chip according to packet encapsulation rules of the brain-inspired computing chip.