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1. A bus decoder of a Military Standard 1553B (MIL-STD-1553B) bus usable for communication between two or more line replaceable units, said bus decoder comprising: a first communication link to a bus controller having an input terminal for receiving two signal outputs of a 1553 transceiver, a first said output signal indicating when a 1553 signal is above ground and a second said output signal indicating when a 1553 signal is below ground; a second communication link to at least one remote terminal; a first RAM buffer and a second RAM buffer, each configured to store and decode one or more respective bus controller to remote terminal interactions, said first RAM buffer and said second RAM buffer being disposed in a ping-pong configuration, whereby said first RAM buffer streams a first bus controller to a first remote terminal interaction from a component while said second RAMbuffer simultaneously decodes a second bus controller to remote terminal interaction; said bus decoder being triggered by an active high signal from either of two input signals from said 1553 transceiver, said bus decoder having a data rate of 1 Mbps and a system clock having a system clock rate ranging from 9.99 MHz to 15.00 MHz with a rising edge and trailing edge, said bus decoder being configured to store decoded information; whereby data output from first said RAM buffer and said second RAM buffer are on said rising edge of said system clock, said data being transmitted with at least 32 bits in parallel starting with a field 0, whereby an active high data valid signal accompanies said data, said bus decoder being further configured to verify a synchronization pattern based upon said MIL-STD-1553B specification to indicate whether or not an incoming signal is a MIL-STD-1553B signal, said system clock having a plurality n of clock states, wherein n is a positive integer greater than 1; and a plurality of n ancillary clocks whereby each said ancillary clock of said plurality of clocks is out of phase with an adjacent ancillary clock by the formula of 360/n degrees, each of said ancillary clocks and said system clock being latchable when a signal to be timestamped goes high as measured at said leading edge to create a plurality of n partial fractional states of said system clock, said plurality of n partial fractional states being summable to provide a system timestamp.
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