US 12,328,128 B2
Sampling circuit, analog-to-digital converter circuit, and semiconductor integrated circuit
Kenta Aruga, Kanagawa (JP); Takeshi Takayama, Kanagawa (JP); and Shota Hino, Kanagawa (JP)
Assigned to SOCIONEXT INC., Yokohama (JP)
Filed by Socionext Inc., Kanagawa (JP)
Filed on Apr. 17, 2023, as Appl. No. 18/301,708.
Application 18/301,708 is a continuation of application No. PCT/JP2020/041165, filed on Nov. 4, 2020.
Prior Publication US 2023/0261664 A1, Aug. 17, 2023
Int. Cl. H03M 1/12 (2006.01); H03M 1/40 (2006.01); H03M 1/46 (2006.01)
CPC H03M 1/1245 (2013.01) [H03M 1/403 (2013.01); H03M 1/462 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A sampling circuit configured to repeatedly perform a series of operations including a reset operation and a sampling operation and sample a differential input voltage during the sampling operation, the sampling circuit comprising:
a first capacitor including a first terminal and a second terminal;
a second capacitor including a third terminal and a fourth terminal;
a first input node configured to receive a first input voltage that is one of the differential input voltage;
a second input node configured to receive a second input voltage that is the other of the differential input voltage;
a first switch circuit configured to be provided between the first input node and the first terminal;
a second switch circuit configured to be provided between the second input node and the third terminal;
a third switch circuit configured to be provided between the first terminal and the third terminal; and
a fourth switch circuit configured to be provided between the second terminal and the fourth terminal, wherein
during the reset operation, the first switch circuit and the second switch circuit are configured to be turned off, and the third switch circuit and the fourth switch circuit are configured to be turned on.