US 12,328,127 B2
System and method for calibrating an analog-to-digital converter using a rational sampling frequency calibration digital-to-analog converter
Albert Molina, Novelda (ES); Kameran Azadet, San Ramon, CA (US); and Martin Clara, Santa Clara, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 22, 2021, as Appl. No. 17/645,461.
Prior Publication US 2023/0198536 A1, Jun. 22, 2023
Int. Cl. H03M 1/10 (2006.01); H03M 1/06 (2006.01); H03M 1/00 (2006.01); H03M 1/68 (2006.01)
CPC H03M 1/1033 (2013.01) [H03M 1/0629 (2013.01); H03M 1/002 (2013.01); H03M 1/1014 (2013.01); H03M 1/68 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An analog-to-digital conversion system, comprising:
a clock generator configured to generate a first clock signal at a first frequency;
an analog-to-digital converter (ADC) configured to convert an input analog signal to a digital signal, wherein the ADC operates based on the first clock signal at the first frequency;
a calibration digital-to-analog converter (DAC) configured to generate an analog reference signal from digital reference data;
a fractional rate clock generator configured to generate a second clock signal from the first clock signal or from a third clock signal, wherein the second clock signal is at a second frequency that is a fractional rate of the first frequency, and the calibration DAC operates at the second frequency, wherein the third clock signal is at a third frequency having an integer frequency relation with the first frequency;
an equalizer configured to process an output of the ADC to remove a distortion incurred by the ADC; and
an adaptation circuitry configured to generate coefficients for the equalizer based on the output of the ADC to the analog reference signal.