US 12,328,121 B2
Systems and methods for configuration of a configuration bit with a value
Dimitri Houssameddine, Sunnyvale, CA (US); Syed M. Alam, Austin, TX (US); and Sanjeev Aggarwal, Scottsdale, AZ (US)
Assigned to Everspin Technologies, Inc., Chandler, AZ (US)
Filed by Everspin Technologies, Inc., Chandler, AZ (US)
Filed on Jul. 31, 2023, as Appl. No. 18/362,704.
Application 18/362,704 is a continuation of application No. 17/652,905, filed on Feb. 28, 2022, granted, now 11,757,451.
Claims priority of provisional application 63/224,637, filed on Jul. 22, 2021.
Prior Publication US 2023/0378958 A1, Nov. 23, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H03K 19/1776 (2020.01); G11C 11/16 (2006.01); G11C 13/00 (2006.01); H03K 19/17724 (2020.01); H03K 19/17784 (2020.01); G06F 21/78 (2013.01)
CPC H03K 19/1776 (2013.01) [G11C 11/1675 (2013.01); G11C 13/0069 (2013.01); H03K 19/17724 (2013.01); H03K 19/17784 (2013.01); G06F 21/78 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A configuration bit, comprising:
a plurality of resistive elements in a first group of resistive elements and a second group of resistive elements, wherein the resistive elements of the first group of resistive elements are arranged in series, wherein the resistive elements of the second group of resistive elements are arranged in series, and wherein the first group of resistive elements are arranged in parallel with the second group of resistive elements; and
an amplifier connected to the first group of resistive elements and the second group of resistive elements, wherein the amplifier is configured to output a signal indicative of data stored in the configuration bit based on a resistance state of each of the plurality of resistive elements, and
wherein at least one resistive element from one or both of the first group of resistive elements or the second group of resistive elements is configured to be shorted.