US 12,328,104 B2
Power amplifier
Yuehang Xu, Chengdu (CN); and Bowen Tang, Chengdu (CN)
Assigned to UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA, Chengdu (CN)
Filed by University of Electronic Science and Technology of China, Chengdu (CN)
Filed on Jul. 28, 2022, as Appl. No. 17/875,465.
Claims priority of application No. 202210362457.1 (CN), filed on Apr. 7, 2022.
Prior Publication US 2023/0327611 A1, Oct. 12, 2023
Int. Cl. H03F 1/42 (2006.01); H03F 1/32 (2006.01); H03F 3/24 (2006.01)
CPC H03F 1/42 (2013.01) [H03F 1/32 (2013.01); H03F 3/245 (2013.01); H03F 2200/36 (2013.01); H03F 2200/451 (2013.01)] 1 Claim
OG exemplary drawing
 
1. A power amplifier, comprising:
1) a preamplifier circuit, the preamplifier circuit comprising a first DC blocking capacitor C1, a first decoupling capacitor C2, a second decoupling capacitor C3, a stabilizing resistor Rill, a first AC blocking resistor RG1, a first input inductor L1, a second input inductor L2, an output inductor L3, a first input microstrip line MLIN1, a second input microstrip line MLIN2, an output microstrip line MLIN3, and a first transistor Q1; and
2) a post amplifier circuit, the post amplifier circuit comprising a first gate microstrip line MLIN4, a second gate microstrip line MLIN5, a third gate microstrip line MLIN6, a fourth gate microstrip line MLIN7, a drain inductor L4, a first drain microstrip line MLIN8, a second drain microstrip line MLIN9, a second AC blocking resistor RG2, a third decoupling capacitor C5, a fourth decoupling capacitor C6, a third DC blocking capacitor C7, an AC blocking inductor L5, a second transistor Q2, a third transistor Q3, and a fourth transistor Q4;
wherein:
a first end of the first DC blocking capacitor C1 acts as an input terminal of the preamplifier circuit, and a second end of the first DC blocking capacitor C1 is connected to the stabilizing resistor Rin, the first input inductor L1, the first input microstrip line MLIN1, and a gate electrode of the first transistor Q1 sequentially;
a first end of the first decoupling capacitor C2 is grounded, and a second end of the first decoupling capacitor C2 is connected to the first AC blocking resistor RG1, the second input inductor L2, the second input microstrip line MLIN2, and the gate electrode of the first transistor Q1 sequentially;
a junction of the first decoupling capacitor C2 and the first AC blocking resistor RG1 is connected to a gate supply voltage Vgs1;
a first end of the second decoupling capacitor C3 is grounded, and a second end of the second decoupling capacitor C3 is connected to the output inductor L3, the output microstrip line MLIN3, and a drain electrode of the first transistor Q1; a junction of the second decoupling capacitor C3 and the output inductor L3 is connected to a drain supply voltage Vds1; and a junction of the output inductor L3 and the output microstrip line MLIN3 acts as an output terminal of the preamplifier circuit;
a second DC blocking capacitor C4 is disposed between the preamplifier circuit and the post amplifier circuit;
a first end of the first gate microstrip line MLIN4 acts as an input terminal of the post amplifier circuit, and a second end of the first gate microstrip line MLIN4 is connected to the second gate microstrip line MLIN5, the third gate microstrip line MLIN6, the fourth gate microstrip line MLIN7, the second AC blocking resistor RG2, and the third decoupling capacitor C5 sequentially; and one end of the third decoupling capacitor C5 is grounded;
a junction of the second AC blocking resistor RG2 and the third decoupling capacitor C5 is connected to a gate supply voltage Vgs2; a junction of first gate microstrip line MLIN4 and the second gate microstrip line MLIN5 is connected to a gate electrode of the second transistor Q2; a junction of the second gate microstrip line MLIN5 and the third gate microstrip line MLIN6 is connected to a gate electrode of the third transistor Q3; a junction of the third gate microstrip line MLIN6 and the fourth gate microstrip line MLIN7 is connected to a gate electrode of the fourth transistor Q4;
the drain inductor L4 is disposed between drain electrodes of the second transistor Q2 and the third transistor Q3;
the first drain microstrip line MLIN8 is disposed between drain electrodes of the third transistor Q3 and the fourth transistor Q4; and
a junction of the first drain microstrip line MLIN8 and the fourth transistor Q4 is connected to a first end of the second drain microstrip line MLIN9; a second end of the second drain microstrip line MLIN9 is connected to first ends of the fourth decoupling capacitor C6, the AC blocking inductor L5, and the third DC blocking capacitor C7; a second end of the fourth decoupling capacitor C6 is grounded; a second end of the AC blocking inductor L5 is connected to a voltage source Vds2; and a second end of the third DC blocking capacitor C7 acts as an output terminal of the post amplifier circuit.