US 12,328,102 B2
Methods and apparatus to improve performance of amplifiers
Vivek Varier, Tucson, AZ (US); Srinivas Pulijala, Tucson, AZ (US); Vadim Ivanov, Tucson, AZ (US); and Jerry Doorenbos, Tucson, AZ (US)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Apr. 28, 2022, as Appl. No. 17/732,385.
Prior Publication US 2023/0353100 A1, Nov. 2, 2023
Int. Cl. H03F 3/16 (2006.01); H03F 1/30 (2006.01)
CPC H03F 1/301 (2013.01) [H03F 3/16 (2013.01); H03F 2200/447 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An amplifier comprising:
folded cascode circuitry having an input and an output;
an input pair of transistors coupled to the input; and
clamp circuitry including:
a first transistor having a first drain, a first source, and a first gate, the first source coupled to the output;
a second transistor having a second drain, a second source, and a second gate, the second drain coupled to the first drain and the second gate coupled to the first drain and second drain;
a third transistor having a third drain, a third source, and a third gate, the third source coupled to the output; and
a fourth transistor having a fourth drain, a fourth source, and a fourth gate, the fourth drain coupled to the third drain and the fourth gate coupled to the third drain and the fourth drain.