US 12,328,099 B2
Apparatus and methods for local oscillator interface circuits with quadrature clock generation and phase correction
Xuesong Jiang, Princeton, NJ (US)
Assigned to Analog Devices, Inc., Wilmington, MA (US)
Filed by Analog Devices, Inc., Wilmington, MA (US)
Filed on Feb. 23, 2023, as Appl. No. 18/173,327.
Prior Publication US 2024/0291431 A1, Aug. 29, 2024
Int. Cl. H03B 5/12 (2006.01); H03B 5/24 (2006.01); H03B 5/36 (2006.01)
CPC H03B 5/124 (2013.01) [H03B 5/24 (2013.01); H03B 5/366 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A semiconductor die comprising:
a first pin configured to receive a non-inverted component of a differential input clock signal from an oscillator external to the semiconductor die;
a second pin configured to receive an inverted component of the differential input clock signal;
an oscillator interface circuit comprising a first controllable resistor and a first controllable capacitor connected in series between the first pin and the second pin, and a second controllable resistor and a second controllable capacitor connected in series between the second pin and the first pin, wherein the first controllable resistor connects to the first controllable capacitor at a first node, and the second controllable resistor connects to the second controllable capacitor at a second node; and
a clock processing circuit having a non-inverted in-phase (I) input connected to the first pin, a non-inverted quadrature-phase (Q) input connected to the first node, an inverted Q input connected to the second node, and an inverted I input connected to the second pin, the clock processing circuit comprising a first single-ended to differential conversion circuit configured to convert a single-ended I signal from one of the first pin or the second pin to a differential I clock signal, and a second single-ended to differential conversion circuit configured to convert a single-ended Q signal from one of the first node or the second node to a differential Q clock signal.