US 12,328,071 B2
Bidirectional direct current converter and control method thereof
Jun Wang, Shanghai (CN); Lei Shi, Shanghai (CN); Yunfeng Liu, Shanghai (CN); and Zhaohui Wang, Nuremberg (DE)
Assigned to HUAWEI DIGITAL POWER TECHNOLOGIES CO., LTD., Shenzhen (CN)
Filed by Huawei Digital Power Technologies Co., Ltd., Shenzhen (CN)
Filed on Dec. 8, 2022, as Appl. No. 18/063,321.
Claims priority of application No. 202111489706.5 (CN), filed on Dec. 8, 2021.
Prior Publication US 2023/0179106 A1, Jun. 8, 2023
Int. Cl. H02M 3/158 (2006.01); H02M 1/00 (2006.01); H02M 3/335 (2006.01); H03K 17/687 (2006.01)
CPC H02M 3/158 (2013.01) [H02M 1/0054 (2021.05); H02M 3/33584 (2013.01); H03K 17/687 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A bidirectional direct current converter comprising:
a first direct current terminal;
a second direct current terminal;
a third direct current terminal;
a fourth direct current terminal;
a first node;
a second node;
a third node;
an inductor comprising:
a first terminal coupled to the first direct current terminal; and
a second terminal coupled to the first node;
a first switching transistor comprising:
a first electrode coupled to the first node; and
a second electrode coupled to the second node;
a second switching transistor comprising:
a third electrode coupled to the second node; and
a fourth electrode coupled to the second direct current terminal and the fourth direct current terminal;
a third switching transistor comprising:
a fifth electrode coupled to the first node; and
a sixth electrode coupled to the third node;
a fourth switching transistor comprising:
a seventh electrode coupled to the third node; and
an eighth electrode coupled to the third direct current terminal;
a capacitor comprising:
a third terminal coupled to the third node; and
a fourth terminal coupled to the second node; and
a controller coupled to the first switching transistor, the second switching transistor, the third switching transistor, and the fourth switching transistor, wherein the controller is configured to:
perform first complementary control on the first switching transistor and the third switching transistor so that the first switching transistor and the third switching transistor cannot be simultaneously turned on or off;
perform second complementary control on the second switching transistor and the fourth switching transistor so that the second switching transistor and the fourth switching transistor cannot be simultaneously turned on or off;
control a first quantity of on times of the second switching transistor to be greater than a second quantity of on times of the first switching transistor in a same cycle to reduce losses of the first switching transistor and the second switching transistor; and
control a third quantity of on times of the fourth switching transistor to be greater than a fourth quantity of on times of the third switching transistor in a same cycle to reduce losses of the third switching transistor and the fourth switching transistor.