US 12,327,996 B2
Power controller
Erik Santiago, La Tour du Crieu (FR); Antoine Fabien Dubois, Austin, TX (US); and Pierre Philippe Calmes, Toulouse (FR)
Assigned to NXP B.V., Eindhoven (NL)
Filed by NXP B.V., Eindhoven (NL)
Filed on Jul. 11, 2023, as Appl. No. 18/350,003.
Claims priority of application No. 22306066 (EP), filed on Jul. 18, 2022.
Prior Publication US 2024/0022065 A1, Jan. 18, 2024
Int. Cl. H02H 7/00 (2006.01); H02H 1/00 (2006.01); H02H 7/20 (2006.01)
CPC H02H 7/20 (2013.01) [H02H 1/0007 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A power controller configured to modulate a load current sent to a load, comprising:
a first chip including a set of higher-power circuits configured to directly modulate the load current sent to the load;
a second chip electrically coupled to the first chip and including a set of lower-power circuits;
wherein the set of higher-power circuits are electrically isolated from the set of lower-power circuits;
a power control path distributed between the first chip and the second chip, and configured to modulate the load current sent to the load;
a diagnostics path distributed between the first chip and the second chip, and configured to monitor the higher-power circuits in the first chip and the lower-power circuits in the second chip for a set of fault conditions;
wherein a portion of the diagnostics path in the second chip includes a plausibility circuit configured to compare a load current commanded by a first portion of the power control path in the second chip to the load current sent to the load by a second portion of the power control path in the first chip; and
wherein the plausibility circuit is configured to transmit a safe-state request if the load current sent to the load is not equivalent to the load current commanded; and
wherein the safe-state request is transmitted in parallel to the load current commanded by the first portion of the power control path in the second chip.