| CPC H01L 25/105 (2013.01) [H01L 23/3128 (2013.01); H01L 23/49894 (2013.01); H01L 23/5383 (2013.01); H01L 23/5385 (2013.01); H01L 23/5386 (2013.01); H01L 24/16 (2013.01); H01L 2224/16227 (2013.01)] | 20 Claims |
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1. A semiconductor package, comprising:
a lower redistribution substrate;
a first lower semiconductor chip mounted on a top surface of the lower redistribution substrate;
a plurality of first lower solder patterns disposed between the lower redistribution substrate and the first lower semiconductor chip;
a plurality of conductive structures disposed on the top surface of the lower redistribution substrate and laterally spaced apart from the first lower semiconductor chip;
a lower molding layer disposed on the top surface of the lower redistribution substrate, the lower molding layer at least partially directly contacting sidewalls of the plurality of conductive structures and sidewalls of the plurality of first lower solder patterns and at least partially covering a top surface of the first lower semiconductor chip;
an upper redistribution substrate disposed on the lower molding layer and the plurality of conductive structures, the upper redistribution substrate being electrically connected to the plurality of conductive structures;
a first upper semiconductor chip mounted on a top surface of the upper redistribution substrate;
a plurality of first upper solder patterns disposed between the upper redistribution substrate and the first upper semiconductor chip; and
an upper molding layer at least partially covering a sidewall of the first upper semiconductor chip and exposing a top surface of the first upper semiconductor chip,
wherein the lower molding layer extends between the lower redistribution substrate and the first lower semiconductor chip,
wherein the upper molding layer extends between the upper redistribution substrate and the first upper semiconductor chip and covers sidewalls of the first upper solder patterns,
wherein a resistivity of the plurality of conductive structures is less than a resistivity of the plurality of first lower solder patterns,
wherein the number of the plurality of conductive structures is the same as or greater than the number of a plurality of first upper chip pads of the first upper semiconductor chip,
wherein the lower redistribution substrate includes:
a first redistribution pattern disposed in a lower dielectric layer, the first redistribution pattern including a first via portion and a first wire portion; and
a first seed pattern disposed on a bottom surface of the first redistribution pattern,
wherein a width of the first via portion at a top surface of the first via portion is greater than a width of the first via portion at a bottom surface of the first via portion, and
wherein the upper redistribution substrate includes:
a second redistribution layer disposed in an upper dielectric layer, the second redistribution layer including a second via pattern and a second wire pattern; and
a second seed pattern disposed on a bottom surface of the second redistribution layer,
wherein a width of the second via pattern at a top surface of the second via pattern is greater than a width of the second via pattern at a bottom surface of the second via pattern.
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