US 12,327,821 B2
Semiconductor package having chip stack
Won-Young Kim, Seoul (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jan. 25, 2024, as Appl. No. 18/422,778.
Application 18/422,778 is a continuation of application No. 17/169,701, filed on Feb. 8, 2021, granted, now 11,916,042.
Application 17/169,701 is a continuation of application No. 16/214,397, filed on Dec. 10, 2018, granted, now 10,930,618.
Claims priority of application No. 10-2018-0012948 (KR), filed on Feb. 1, 2018.
Prior Publication US 2024/0186293 A1, Jun. 6, 2024
Int. Cl. H01L 23/48 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2023.01); H01L 29/40 (2006.01)
CPC H01L 25/0657 (2013.01) [H01L 24/32 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48145 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73265 (2013.01); H01L 2225/06506 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06562 (2013.01); H01L 2924/00014 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a substrate;
a first semiconductor chip on the substrate, the first semiconductor chip having a first region and a second region in a plan view;
a second semiconductor chip on a top surface of the second region of the first semiconductor chip, the second semiconductor chip exposing the first region and completely covering the second region;
a first signal connector on a top surface of the first region of the first semiconductor chip, the first signal connector being coupled to the first semiconductor chip and the substrate;
a second signal connector on the top surface of the first region of the first semiconductor chip, the second signal connector being coupled to the second semiconductor chip and the first semiconductor chip;
a third connector for power or ground on the top surface of the second region of the first semiconductor chip, the third connector being coupled to the substrate; and
an insulation pattern on the substrate and covering a side surface of the first semiconductor chip,
wherein each of the first signal connector and the third connector includes a wiring line pattern, and
wherein the first signal connector and the third connector cover a part of the insulation pattern.