| CPC H01L 25/0652 (2013.01) [H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/50 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/80006 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06586 (2013.01)] | 20 Claims |
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1. A method comprising:
attaching a first die and a second die to a first wafer, the first wafer comprising:
a first carrier substrate; and
a first interconnect structure comprising first dielectric layers and first conductive features embedded in the first dielectric layers;
encapsulating the first die and the second die in a first encapsulant;
attaching a third die to the first die and a fourth die to the second die, the third die being electrically connected to the first die, the fourth die being electrically connected to the second die;
encapsulating the third die and the fourth die in a second encapsulant;
attaching a second wafer to the third die and the fourth die, the second wafer comprising:
a second carrier substrate; and
a second interconnect structure comprising second dielectric layers and second conductive features embedded in the second dielectric layers;
removing the first carrier substrate;
patterning the first dielectric layers to expose conductive features of the first die and the second die; and
forming external connectors through the first dielectric layers, the external connectors being electrically connected to corresponding ones of the conductive features of the first die and the second die.
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