	US 12,327,811 B2
	Ion implantation with annealing for substrate cutting
Huicheng Chang, Tainan (TW); Jyh-Cherng Sheu, Hsinchu (TW); Chen-Fong Tsai, Hsinchu (TW); Yun Chen Teng, New Taipei (TW); Han-De Chen, Hsinchu (TW); and Yee-Chia Yeo, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Dec. 20, 2023, as Appl. No. 18/390,439.
Application 18/390,439 is a continuation of application No. 17/497,050, filed on Oct. 8, 2021, granted, now 11,855,040.
Claims priority of provisional application 63/187,558, filed on May 12, 2021.
Prior Publication US 2024/0120314 A1, Apr. 11, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/265 (2006.01); H01L 21/683 (2006.01); H01L 21/78 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01)

CPC H01L 24/83 (2013.01) [H01L 21/265 (2013.01); H01L 21/6835 (2013.01); H01L 21/7806 (2013.01); H01L 25/50 (2013.01)]

20 Claims

1. A method comprising:

forming a transistor structure of a device on a first semiconductor substrate;

forming a front-side interconnect structure over a front side of the transistor structure;

forming a bonding layer on a carrier substrate;

implanting ions into the carrier substrate through the bonding layer to form an implantation region of the carrier substrate;

bonding the carrier substrate to the front-side interconnect structure;

removing the carrier substrate, wherein removing the carrier substrate comprises:

applying an annealing process to separate the implantation region of the carrier substrate and a remainder region of the carrier substrate, the annealing process comprising applying a pulsed laser to the implantation region of the carrier substrate, wherein an energy density of the pulsed laser is at least 600 mJ/cm², and wherein a maximum device temperature of the device during the annealing process is at most 400° C.; and

forming a back-side interconnect structure over a back side of the transistor structure.