US 12,327,809 B2
Vertically stacked and bonded memory arrays
Abhishek A. Sharma, Hillsboro, OR (US); Wilfred Gomes, Portland, OR (US); and Mauro J. Kobrinsky, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 23, 2021, as Appl. No. 17/355,793.
Prior Publication US 2022/0415841 A1, Dec. 29, 2022
Int. Cl. H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H10B 12/00 (2023.01)
CPC H01L 24/32 (2013.01) [H01L 24/83 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H10B 12/315 (2023.02); H10B 12/34 (2023.02); H01L 2224/32145 (2013.01); H01L 2224/83894 (2013.01); H01L 2924/1436 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) device, comprising:
a first memory layer comprising a first support structure and a first plurality of memory cells;
a second memory layer comprising a second support structure and a second plurality of memory cells;
a first bonding interface coupling the second support structure of the second memory layer to the first memory layer, the first bonding interface comprising a bonding material to bond the second memory layer to the first memory layer;
a first bit-line coupled to a portion of the first plurality of memory cells;
a second bit-line coupled to a portion of the second plurality of memory cells; and
a via coupled to the second bit-line, wherein the via extends through the second support structure and the first bonding interface.