US 12,327,792 B2
Semiconductor structure and manufacturing methods thereof
Bo-Jiun Lin, Hsinchu County (TW); and Tung-Ying Lee, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jan. 21, 2022, as Appl. No. 17/580,648.
Claims priority of provisional application 63/214,749, filed on Jun. 24, 2021.
Prior Publication US 2022/0415817 A1, Dec. 29, 2022
Int. Cl. H01L 23/532 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01)
CPC H01L 23/53223 (2013.01) [H01L 21/7685 (2013.01); H01L 21/76864 (2013.01); H01L 23/5226 (2013.01); H01L 23/53238 (2013.01); H01L 21/76846 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a substrate having a semiconductor device; and
an interconnect, disposed over the substrate and electrically coupled to the semiconductor device, comprising:
a metallization layer, disposed over the substrate, and comprising a via portion and a line portion connecting to the via portion;
a capping layer, covering the line portion, wherein the line portion is sandwiched between the via portion and the capping layer, and the capping layer comprises a plurality of sub-layers; and
a dielectric layer, laterally covering the metallization layer,
wherein:
the plurality of sub-layers independently comprise a material comprising MXn1, wherein M is a transition metal selected from the groups IVB, VB, or VIB of the periodic table, X is an element selected from a group consisting of sulfur, selenium, and tellurium, and n1 is in a range of 0.5-2, or
the plurality of sub-layers independently comprise a material comprising Tan2Sn3, wherein n2 is in a range of 1-2, and n3 is in a range of 2-5.