| CPC H01L 23/5226 (2013.01) [H01L 21/76802 (2013.01); H01L 21/76843 (2013.01); H01L 21/76877 (2013.01); H01L 23/53266 (2013.01); H01L 23/53271 (2013.01); H10B 41/27 (2023.02); H10B 43/27 (2023.02)] | 8 Claims |

|
1. A semiconductor memory device comprising:
a first stacked body including a plurality of first conductive layers and a plurality of insulating films alternatively stacked in a first direction, the plurality of first conductive layers each including tungsten;
a second stacked body provided adjacent to the first stacked body in a second direction and including a plurality of second conductive layers and the plurality of insulating films alternatively stacked in the first direction, the plurality of second conductive layers being respectively disposed in a same level in the first direction as a corresponding layer of the plurality of first conductive layers, the plurality of second conductive layers including a silicon containing an impurity, the second direction crossing the first direction;
a semiconductor layer extending in the first direction through an inside of the first stacked body;
a charge storage layer arranged between the plurality of first conductive layers and the semiconductor layer in the first stacked body;
a plurality of contact plugs respectively provided on a corresponding layer of the plurality of second conductive layers; and
the plurality of first conductive layers, which include the tungsten, are in direct contact on a same plane with the plurality of second conductive layers, which include the silicon containing the impurity, respectively.
|