US 12,327,775 B2
Thermal performance in hybrid bonded 3D die stacks
Feras Eid, Chandler, AZ (US); Adel Elsherbini, Tempe, AZ (US); Johanna Swan, Scottsdale, AZ (US); Shawna Liff, Scottsdale, AZ (US); Aleksandar Aleksov, Chandler, AZ (US); and Julien Sebot, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 25, 2021, as Appl. No. 17/358,361.
Prior Publication US 2022/0415743 A1, Dec. 29, 2022
Int. Cl. H01L 23/36 (2006.01); H01L 21/50 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2023.01); H10D 88/00 (2025.01)
CPC H01L 23/36 (2013.01) [H01L 21/50 (2013.01); H01L 24/95 (2013.01); H01L 25/0657 (2013.01); H10D 88/00 (2025.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) structure, comprising:
one or more first IC dies in a first layer of a 3D die stack;
a plurality of second IC dies in a second layer of the 3D die stack each direct bonded to at least one of the one or more first IC dies via a plurality of first composite metal structures between the second IC dies and the one or more first IC dies and embedded in a first dielectric structure; and
a plurality of thermal dies in the second layer of the 3D die stack each direct bonded to at least one of the one or more first IC dies via a plurality of second composite metal structures between the thermal dies and the one or more first IC dies and embedded in a second dielectric structure, wherein the thermal dies each has a greater thermal conductivity than each of the second IC dies or comprises an active thermal cooling die.