US 12,327,773 B2
Package with underfill containment barrier
Rahul Jain, Gilbert, AZ (US); Kyu Oh Lee, Chandler, AZ (US); Siddharth K. Alur, Chandler, AZ (US); Wei-Lun K. Jen, Chandler, AZ (US); Vipul V. Mehta, Chandler, AZ (US); Ashish Dhall, Chandler, AZ (US); Sri Chaitra J. Chavali, Chandler, AZ (US); Rahul N. Manepalli, Chandler, AZ (US); Amruthavalli P. Alur, Tempe, AZ (US); and Sai Vadlamani, Gilbert, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jan. 17, 2024, as Appl. No. 18/415,268.
Application 18/415,268 is a continuation of application No. 18/133,868, filed on Apr. 12, 2023, granted, now 11,935,805.
Application 18/133,868 is a continuation of application No. 17/459,993, filed on Aug. 27, 2021, granted, now 11,664,290, issued on May 30, 2023.
Application 17/459,993 is a continuation of application No. 16/464,547, granted, now 11,158,558, issued on Oct. 26, 2021, previously published as PCT/US2016/069321, filed on Dec. 29, 2016.
Prior Publication US 2024/0186202 A1, Jun. 6, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/13 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 23/532 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/3185 (2013.01) [H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 21/563 (2013.01); H01L 23/3128 (2013.01); H01L 23/49816 (2013.01); H01L 23/53295 (2013.01); H01L 23/5381 (2013.01); H01L 23/5383 (2013.01); H01L 23/5386 (2013.01); H01L 24/06 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/81 (2013.01); H01L 25/0655 (2013.01); H01L 25/0657 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/81 (2013.01); H01L 2224/83051 (2013.01); H01L 2924/18161 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a substrate;
a first die and a second die over a surface of the substrate, the second die laterally spaced apart from the first die;
an interconnect bridge coupled to the substrate, the interconnect bridge beneath the first die and the second die, the interconnect bridge partially within a footprint of the first die and partially within a footprint of the second die, and the interconnect bridge coupled to the first die and the second die;
a metal structure on the surface of the substrate, the metal structure extending away from the surface of the substrate, and the metal structure laterally surrounding the first die and the second die; and
a dielectric material laterally between the metal structure and the first die or the second die, wherein the dielectric material does not extend beyond the metal structure.