US 12,327,772 B2
Semiconductor package including stress-reduction structures and methods of forming the same
Shu-Shen Yeh, Taoyuan (TW); Yu-Sheng Lin, Zhubei (TW); Ming-Chih Yew, Hsinchu (TW); Po-Yao Lin, Zhudong Township (TW); Shin-Puu Jeng, Po-Shan Village (TW); and Chin-Hua Wang, New Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed on May 20, 2022, as Appl. No. 17/749,198.
Claims priority of provisional application 63/274,972, filed on Nov. 3, 2021.
Prior Publication US 2023/0137164 A1, May 4, 2023
Int. Cl. H01L 23/10 (2006.01); H01L 23/16 (2006.01); H01L 23/467 (2006.01)
CPC H01L 23/10 (2013.01) [H01L 23/16 (2013.01); H01L 23/467 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a package substrate;
semiconductor devices disposed on the package substrate;
a package ring disposed on a perimeter of the package substrate surrounding the semiconductor devices;
a cover disposed over the package ring and the semiconductor devices;
a cover adhesive bonding the cover to the package ring; and
a stress-reduction structure comprising first channels formed in an upper surface of the package ring and second channels formed in a lower surface of a portion of the cover that overlaps with the first channels in a vertical direction perpendicular to a plane of the package substrate,
wherein the stress-reduction structure is free from the cover adhesive.