	US 12,327,730 B2
	Two-color self-aligned double patterning (SADP) to yield static random access memory (SRAM) and dense logic
Fee Li Lie, Albany, NY (US); Dongbing Shao, Wappingers Falls, NY (US); Robert C. Wong, Poughkeepsie, NY (US); and Yongan Xu, Albany, NY (US)
Assigned to Adeia Semiconductor Solutions LLC, San Jose, CA (US)
Filed by Adeia Semiconductor Solutions LLC, San Jose, CA (US)
Filed on Mar. 21, 2024, as Appl. No. 18/612,807.
Application 18/612,807 is a continuation of application No. 18/201,061, filed on May 23, 2023, granted, now 11,978,639.
Application 18/201,061 is a continuation of application No. 17/360,819, filed on Jun. 28, 2021, granted, now 11,699,591, issued on Jul. 11, 2023.
Application 17/360,819 is a continuation of application No. 16/796,614, filed on Feb. 20, 2020, granted, now 11,062,911, issued on Jul. 13, 2021.
Application 16/796,614 is a continuation of application No. 15/842,841, filed on Dec. 14, 2017, granted, now 10,573,528, issued on Feb. 25, 2020.
Prior Publication US 2024/0258113 A1, Aug. 1, 2024
Int. Cl. H01L 21/308 (2006.01); H01L 21/033 (2006.01); H01L 21/3065 (2006.01); H01L 21/311 (2006.01); H10D 30/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01); H10B 10/00 (2023.01); H10D 30/62 (2025.01)

CPC H01L 21/3086 (2013.01) [H01L 21/0332 (2013.01); H01L 21/0335 (2013.01); H01L 21/0337 (2013.01); H01L 21/3065 (2013.01); H01L 21/3081 (2013.01); H01L 21/3085 (2013.01); H01L 21/31116 (2013.01); H10D 30/0243 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01); H10D 84/834 (2025.01); H10B 10/12 (2023.02); H10B 10/18 (2023.02); H10D 30/024 (2025.01); H10D 30/62 (2025.01)]

22 Claims

1. A method of forming a semiconductor region, the method comprising:

providing a first set of features corresponding to a first lithography process, each feature of the first set of features having a first width;

subsequent to providing the first set of features, forming a second set of features corresponding to a second lithography process;

forming a first set of mandrels corresponding to the first set of features and a second set of mandrels corresponding to the second set of features, wherein a first mandrel of the first set of mandrels is adjacent to a first mandrel of the second set of mandrels;

concurrently forming spacers on the first and second sets of mandrels, wherein the mandrels of the first set of mandrels have substantially the first width when the spacers are formed;

removing the first and second sets of mandrels to form an intermediate fin pattern, the intermediate fin pattern comprising:

first and second intermediate fins corresponding to spacers on opposite sides of the first mandrel of the first set of mandrels; and

third and fourth intermediate fins corresponding to spacers on opposite sides of the first mandrel of the second set of mandrels, wherein the second and third intermediate fins are adjacent intermediate fins; and

performing an etch to transfer the intermediate fin pattern to a substrate to form first, second, third, and fourth semiconductor fins.