US 12,327,612 B2
Semiconductor system for performing a data alignment operation
Hyun Seung Kim, Icheon-si (KR); and Hyeong Soo Jeong, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Jun. 21, 2023, as Appl. No. 18/339,101.
Claims priority of application No. 10-2023-0021045 (KR), filed on Feb. 16, 2023.
Prior Publication US 2024/0282352 A1, Aug. 22, 2024
Int. Cl. G11C 7/22 (2006.01); G11C 7/10 (2006.01)
CPC G11C 7/222 (2013.01) [G11C 7/1093 (2013.01); G11C 7/1096 (2013.01)] 25 Claims
OG exemplary drawing
 
1. A semiconductor system comprising:
a first memory device and a second memory device configured to share a first transmission line from which a write clock is received and a second transmission line from which data is received,
wherein the first memory device receives the data in synchronization with first, second, third, and fourth internal clocks that are generated by dividing a frequency of the write clock, and selectively aligns and stores at least some of the data that is received in synchronization with the first to fourth internal clocks based on timing at which the data is synchronized with the write clock, and
the second memory device receives the data in synchronization with fifth, sixth, seventh, and eighth internal clocks that are generated by dividing the frequency of the write clock, and selectively aligns and stores at least some of the data that is received in synchronization with the fifth to eighth internal clocks based on timing at which the data is synchronized with the write clock.