US 12,327,610 B2
Data receiving circuit, data receiving system and memory device
Feng Lin, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Jan. 14, 2023, as Appl. No. 18/154,794.
Application 18/154,794 is a continuation of application No. PCT/CN2022/104759, filed on Jul. 8, 2022.
Claims priority of application No. 202210726620.8 (CN), filed on Jun. 23, 2022.
Prior Publication US 2023/0420015 A1, Dec. 28, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 7/00 (2006.01); G11C 7/06 (2006.01); G11C 7/20 (2006.01); G11C 7/22 (2006.01)
CPC G11C 7/20 (2013.01) [G11C 7/067 (2013.01); G11C 7/222 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A data receiving circuit, comprising:
a first amplifier circuit configured to receive a data signal, a first reference signal and a second reference signal, perform a first comparison between the data signal and the first reference signal and output a first signal pair as a result of the first comparison, perform a second comparison between the data signal and the second reference signal, and output a second signal pair as a result of the second comparison;
wherein a level value of the first reference signal is different from a level value of the second reference signal, the first signal pair comprising a first signal and a second signal, and the second signal pair comprising a third signal and a fourth signal; and
a second amplifier circuit configured to select to receive the first signal pair or the second signal pair as input signal pairs based on a feedback signal, amplify a voltage difference between the input signal pairs, and output a first output signal and a second output signal as a result of the amplification, wherein the feedback signal is obtained based on previously received data; and,
wherein the second amplifier circuit comprises:
a first input subcircuit connected to a seventh node and an eighth node, the first input subcircuit being configured to be turned on in response to the feedback signal to receive the first signal pair and compare the first signal pair, and respectively provide a signal to the seventh node and the eighth node;
a second input subcircuit connected to the seventh node and the eighth node, the second input subcircuit being configured to be turned on in response to the feedback signal to receive the second signal pair and compare the second signal pair, and provide a signal to the seventh node and the eighth node, respectively,
wherein either of the first input subcircuit and the second input subcircuit is selectively turned on based on the feedback signal; and
a latch subcircuit connected to the seventh node and the eighth node, the latch subcircuit being configured to amplify and latch a signal of the seventh node and a signal of the eighth node, and output the first output signal and the second output signal respectively through a first output node and a second output node.