| CPC G11C 7/1069 (2013.01) [G11C 7/1063 (2013.01)] | 20 Claims |
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1. A semiconductor device comprising:
a chip selection signal receiver configured to receive, from an external memory controller, a chip selection signal activating to a state in which communication is possible with the external memory controller;
a data signal receiver configured to receive a command and an address from the external memory controller;
an operation controller configured to perform an internal operation according to the command and the address received through the data signal receiver while the chip selection signal is input; and
an internal signal generator configured to output an inactivated internal chip selection signal blocking transferal of the chip selection signal to the operation controller when a command other than a command requesting an output of data is received while the internal operation is performed.
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