US 12,327,601 B2
Method and apparatus for power saving in semiconductor devices
Jian Luo, Wuhan (CN); and Zhuqin Duan, Wuhan (CN)
Assigned to Yangtze Memory Technologies Co., Ltd., Wuhan (CN)
Filed by Yangtze Memory Technologies Co., Ltd., Hubei (CN)
Filed on Mar. 20, 2024, as Appl. No. 18/610,880.
Application 18/610,880 is a continuation of application No. 17/472,542, filed on Sep. 10, 2021, granted, now 11,967,393.
Application 17/472,542 is a continuation of application No. PCT/CN2021/095709, filed on May 25, 2021.
Prior Publication US 2024/0233781 A1, Jul. 11, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 5/14 (2006.01); G06F 1/06 (2006.01); G11C 11/40 (2006.01)
CPC G11C 5/148 (2013.01) [G06F 1/06 (2013.01); G11C 11/40 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a memory cell array comprising memory cells; and
peripheral circuitry coupled with the memory cell array and comprising:
a clock gating circuit comprising a first input terminal, a second input terminal, and a first output terminal, the first input terminal coupled to a clock source, the first output terminal configured to output a gated clock signal based on a clock signal from the clock source and a clock enable signal;
a polling module comprising a third input terminal, a fourth input terminal, and a second output terminal, the third input terminal configured to receive a wakeup control, the fourth input terminal configured to receive a disable control, the second output terminal coupled to the second input terminal of the clock gating circuit and configured to output the clock enable signal based on the wakeup control or the disable control; and
a processing core comprising a fifth input terminal and a third output terminal, the fifth input terminal coupled to the first output terminal of the clock gating circuit, the third output terminal coupled to the third input terminal of the polling module and configured to output the disable control during an operation.