US 12,327,599 B2
Memory with scan chain testing of column redundancy logic and multiplexing
Rahul Sahu, Bangalore (IN); Sharad Kumar Gupta, Bangalore (IN); Jung Pill Kim, San Diego, CA (US); Chulmin Jung, San Diego, CA (US); and Jais Abraham, Bangalore (IN)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Mar. 14, 2024, as Appl. No. 18/605,685.
Application 18/605,685 is a division of application No. 17/364,738, filed on Jun. 30, 2021, granted, now 11,935,606.
Prior Publication US 2024/0221853 A1, Jul. 4, 2024
Int. Cl. G11C 29/10 (2006.01); G11C 7/06 (2006.01); G11C 7/10 (2006.01)
CPC G11C 29/10 (2013.01) [G11C 7/06 (2013.01); G11C 7/106 (2013.01); G11C 7/1096 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A memory, comprising:
a plurality of columns, each column including:
a bit line;
a complement bit line;
a first read multiplexer transistor coupled to the bit line and having a read terminal;
a second read multiplexer transistor coupled to the complement bit line and having a complement read terminal;
a sense amplifier having a first input terminal coupled to the read terminal and a second input terminal coupled to the complement read terminal;
a read column redundancy multiplexer having a first input terminal coupled to an output terminal of the sense amplifier and having a second input terminal coupled to a sense amplifier in an adjacent column; and
a data output latch having an input terminal coupled to an output terminal of the read column redundancy multiplexer through a direct electrical connection.