US 12,327,596 B2
Semiconductor storage device
Ryota Hirai, Chigasaki Kanagawa (JP); Daisuke Arizono, Yokohama Kanagawa (JP); Yasuhiro Shiino, Fujisawa Kanagawa (JP); and Takuya Kusaka, Yokohama Kanagawa (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Sep. 1, 2021, as Appl. No. 17/463,693.
Claims priority of application No. 2021-024460 (JP), filed on Feb. 18, 2021.
Prior Publication US 2022/0262444 A1, Aug. 18, 2022
Int. Cl. G11C 16/08 (2006.01); G11C 16/04 (2006.01); G11C 16/12 (2006.01); G11C 16/26 (2006.01); G11C 16/30 (2006.01); G11C 16/32 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/349 (2013.01) [G11C 16/0433 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/12 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01); G11C 16/32 (2013.01); G11C 16/3404 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A semiconductor storage device comprising:
a memory cell array including a plurality of memory cell transistors;
a plurality of word lines respectively connected to a plurality of gates of the plurality of memory cell transistors;
a voltage detection circuit connected to at least one of the plurality of word lines; and
a control circuit configured to detect, when a writing voltage is applied to a selected word line selected from among the plurality of word lines at a time of data writing to the memory cell array, a voltage of the selected word line through the voltage detection circuit, and to perform a determination as to whether the detected voltage obtained through the detection has reached a predetermined value,
wherein a setting of a number of times that the control circuit detects the voltage of the selected word line through the voltage detection circuit is changeable.