US 12,327,595 B2
Shortened single-level cell memory programming
Leo Raimondo, Avezzano (IT); Federica Paolini, Francavilla al Mare (IT); Umberto Siciliani, Rubano (IT); Violante Moschiano, Avezzano (IT); Gianfranco Valeri, Pescina (IT); Davide Esposito, Silvi (IT); and Walter Di Francesco, Avezzano (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Oct. 28, 2022, as Appl. No. 17/976,423.
Claims priority of provisional application 63/275,865, filed on Nov. 4, 2021.
Prior Publication US 2023/0134281 A1, May 4, 2023
Int. Cl. G11C 16/34 (2006.01); G11C 16/10 (2006.01)
CPC G11C 16/3459 (2013.01) [G11C 16/102 (2013.01)] 17 Claims
OG exemplary drawing
 
7. A method comprising:
causing, by control logic of a memory device, hardware initialization of a plurality of sub-blocks that are to be programmed within an array of memory cells configured as single-level cell memory;
causing, by the control logic, a first sub-block of the plurality of sub-blocks to be preconditioned for a program operation;
causing, by the control logic, a plurality of pages of data to be programmed to respective ones of the plurality of sub-blocks, comprising:
(i) causing a program pulse to be sent to the first sub-block to program a first page of the plurality of pages of data to the first sub-block;
(ii) causing a recovery operation to be performed at the first sub-block; and
(iii) causing a reduced seed operation to be performed at a second sub-block of the plurality of sub-blocks to precondition the second sub-block for programming; and
selectively causing, by the control logic, a program verify to be performed on memory cells of the plurality of sub-blocks after programming the plurality of pages of data.