US 12,327,593 B2
Memory device and operating method of the memory device
Nam Cheol Jeon, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Dec. 9, 2022, as Appl. No. 18/078,620.
Claims priority of application No. 10-2022-0095615 (KR), filed on Aug. 1, 2022.
Prior Publication US 2024/0038304 A1, Feb. 1, 2024
Int. Cl. G11C 8/00 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/30 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/08 (2013.01) [G11C 16/0433 (2013.01); G11C 16/30 (2013.01); G11C 16/3404 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A memory device comprising:
a first memory block and a second memory block each including a plurality of memory cells;
a voltage generator configured to apply operating voltages to first global lines, selectively apply a positive voltage to global select lines included in second global lines while the operating voltages are applied, and apply a ground voltage to the second global lines except the global select lines included in the second global lines; and
a row decoder configured to turn on first pass switches between first local lines connected to the first memory block and the first global lines and configured to turn off second pass switches between second local lines connected to the second memory block and the second global lines.